Appeal No. 96-0511
Application 08/158,837
10b. These complementary data values permit testing for
interference between the cells in each memory (col. 2, line 68
to col. 3, line 6). During the testing mode of operation, the
four test data values are written simultaneously into all four
memory cells (col. 2, lines 40-48). The stored data values
are then read out simultaneously, with the values on data
buses DB2 and DB4 being directly coupled to terminals TO2 and
TO4 of circuit 62 and with the values on DB1 and DB3 being
coupled to terminals TO1 and TO3 via inverters 64 and 66 (Fig.
1B) so that the voltages at all four terminals will have the
same value if no memory cell is defective. Referring to
Figure 5, which shows the details of circuit 62, the data on
terminals TO1-TO4 (TO2 and TO4 are identified as DB2 and DB4
in the figure) and their complements are compared to determine
whether the data on terminals TO1-TO4 is all the same; if they
are not, a high level signal appears at the output of the
circuit (col. 19, line 67 to col. 20, line 8). The foregoing
process is then repeated for each remaining group of four
memory cells (col. 22, lines 8-40).
Comparing claim 23 to Tanigawa, the examiner appears to
read
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