Appeal No. 96-0511
Application 08/158,837
cycle by shifting the data along the columns using the
coupling transistors T' (col. 7, lines 17-21). This may be
done by using the on-chip refresh address counter to cycle
through the 512 row addresses, while applying externally
generated column addresses in a short cycle, or column
addresses from an on-chip column address counter (col. 7,
lines 21-26). A clearer description of this procedure appears
in Childers' claim 14, which reads as follows:
14. A method of writing data into a semiconductor
device containing an array of rows and columns of memory
cells, comprising the steps of:
writing a data pattern to one of said columns by
sequentially addressing said rows while coupling data
bits to the columns from a terminal of the device, then
writing said data pattern to all other columns of
said device by sequentially addressing said rows while
coupling said one column to a first adjacent column, then
coupling said first adjacent column to a second adjacent
column, until all columns are written into. [Emphasis
added.]
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