Appeal No. 96-0511
Application 08/158,837
For data other than test data, this circuitry writes into and
reads from one memory cell at a time, using a selected one of
data buses DB1-DB4 (see, e.g., col. 6, lines 41-54; col. 7,
lines 4-11). The memory testing circuitry shown in Figure 1B,
which is rendered operative by a high test enable signal TE
(col. 12, lines 1-8), uses all four data buses at once to
simultaneously write test data into and then to simultaneously
read the stored data from four memory cells (col. 2, lines 40-
48). This circuitry includes circuit elements 56, 58 and 50
for generating complementary test data values to be applied to
data buses DB1-DB4. Element 56, which is shown in detail in
Figure 3, generates at each of four output terminals TI1-TI4,
a voltage representing the input test data (col. 14, line 63
to col. 15, line 5). Terminals TI2 and TI4 are directly
connected to data buses DB2 and DB4, respectively, whereas
terminals TI and TI3 are connected to data buses DB1 and DB3,
respectively, through inverters 58 and 60. As a result, the
test data values on buses DB1 and DB2, which are to be applied
to a pair of row-adjacent memory cells in memory 10a, are
complementary, as are the test data values on DB3 and DB4, to
be applied to a pair of row-adjacent memory cells in memory
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Last modified: November 3, 2007