Appeal No. 96-0511
Application 08/158,837
and are thus entitled to be construed in accordance with § 112
¶ 6, Appellants do not rely on § 112 ¶ 6 to distinguish these
limitations from the prior art.
The references relied on by the examiner are as follows:
Tanigawa 4,888,772 Dec. 19, 1989
Chiders 4,670,878 Jun. 2, 1987
Furutani et al. 4,817,056 Mar. 28, 1989
Claims 23-26, 32, 39, and 53 stand rejected under § 103
as unpatentable over Tanigawa in view of Childers. Claims 40-
43, 50-52, and 54-60 stand rejected under § 103 as
unpatentable over Tanigawa in view of Childers and Furutani.
Tanigawa discloses a memory testing circuit that permits
complementary test data to be used to test adjacent memory
cells for interference defects in a memory has two memory
parts 10a and 10b (col. 11, lines 64-68). Referring to Figure
1A, a single column select signal (e.g., CS1) issued by column
address decoder 14 closes four selector switches (S , S , S ,11 12 21
S ), thereby connecting four bit lines (D , D , D , D ) to22 11 12 21 22
data buses DB1, DB2, DB3, and DB4. Figure 1C shows the
circuitry for controlling the writing of data into and reading
of data from the memories.
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