Appeal No. 96-0511
Application 08/158,837
original input data signal D " (col. 7, lines 11-17). The
IN
meaning of this passage in Tanigawa is unclear, because
Tanigawa's drawings and detailed description of the testing
procedure nowhere show or describe a comparison of D with
out
D . Instead, as noted above, Tanigawa detects defective
IN
memory cells by examining the voltages at terminals TO1-TO4
(Fig.5), all of which are derived from the fetched data
appearing on DB1-DB4, to determine whether they are all the
same; if they are not, there is a defect in one of the four
memory cells being tested. For this reason, Tanigawa does not
inherently employ "temporarily storing" means for holding the
test data until it can be compared to the fetched data, as
required by claim 23. As will appear, neither this deficiency
in Tanigawa nor the other deficiencies discussed below are
remedied by Childers or Furutani.
The examiner concedes that Tanigawa fails to disclose
claim 23's "means for simultaneously transferring said
external data in each single row of said preliminary memory
cells . . . to a corresponding single row of said plurality of
memory cells . . . via said bit lines connecting said
plurality of memory cells and preliminary memory cells." For
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