Appeal No. 96-0511
Application 08/158,837
1) are applied to lines N3 and N4 of each bit line pair for
writing the test data into the memory cells of a row of the
preliminary memory (selected by a "spare" word line) or into
the cells of a row of the normal memory (selected by a
"normal" word line) (Spec. at p. 72, lines 9-18). At the same
time, the test data is latched into registers 3 for each bit
line pair (Spec. at p. 72, lines 19-21). Next, the word line
is selected to read out the stored test data, which is then
compared by match detection circuits 2 to the data values
stored in respective registers 3 and the results are issued on
output line DS (Spec. at p. 72, lines 21 to p. 73, line 4).
Because each bit line pair has its own register 3 and match
detection circuit 2, different test data can be used to test
row-adjacent memory cells (Spec. at p. 73, lines 10-15).
Providing plural registers for each bit line pair permits
different data patterns to be used to test different rows
(Spec. at 74, lines 2-9).
Figure 11 shows an alternative embodiment having two
separate memories 1 and 2 of normal memory cells and
associated memories 11 and 13 of preliminary memory cells.
Identical test data are written into one or more rows of
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Last modified: November 3, 2007