Appeal No. 96-0511
Application 08/158,837
55 under § 112, second paragraph was withdrawn in the Answer
(at p. 2). Claims 9 and 10 have been allowed. We reverse.
The invention relates to a semiconductor memory structure
that permits different test data to be written into and read
out of row-adjacent memory cells in order to detect
interference between those memory cells (Spec. at p. 13, lines
1-5; p. 14, lines 7-11). Figure 1 shows a semiconductor
memory device of the type having a "preliminary" memory 202
with rows of memory cells which can be substituted for
defective memory cells in a "normal" memory 201 (Spec. at p.
23, lines 6-12). The two memories have different word line
(i.e., "word lines" WL -WL ans "spare word lines" SWL -SWL )1 m 1 2
but share the same bit line pairs (B /B -B /B ). The device
1 1 l l
shown in Figure 1 differs from the prior art by being
constructed so as to permit an entire row of data to be
transferred simultaneously in either direction between the
preliminary memory and the normal memory during one write
cycle (Spec. at p. 27, lines 3-9). Specifically,
preliminary row decoder 203b and normal row decoder 203a
are controlled in response to a spare enable signal SE
and an inversion signal SE thereof, so that they can be
enabled alternately. When preliminary row encoder 203b
is first enabled, spare word line SWL1 or SWL2 selected
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