Appeal No. 1998-1365 Page 2
Application No. 08/663,969
BACKGROUND
A computer’s clock rate is a prime determinant of its
overall processing speed. A clock typically operates at a
frequency of 50-150 MHZ. To achieve higher performance, a
microprocessor may generate an on-chip clock signal by
multiplying the frequency of an off-chip clock source.
Accordingly, a 50-MHZ off-chip source can be used to generate
on-chip clocking of 200 MHZ. Unfortunately, techniques to
check on-chip clocking during manufacturing are complex and
time consuming.
The invention at issue in this appeal is a test circuit
for determining whether an on-chip clock signal is a correct
multiple of a reference clock signal and whether the two
signals are in-phase. Specifically, the test circuit, a
1(...continued)
181 (Bd. Pat. App. & Int. 1958) (citing Ex parte Charch, 102
USPQ 363, 364 (Bd. Pat. App. & Int. 1954) and Ex parte Hill,
93 USPQ 45, 46 (Bd. Pat. App. & Int. 1952)). In the answer,
the examiner neither repeats nor references the final
rejection of claims 29 and 38 as obvious over Marshall in view
of Vanderspool. (Final Rejection at 2.) Therefore, we
conclude that the rejection of those claims under 35 U.S.C. §
103 has been withdrawn.
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