Appeal No. 1998-1365 Page 3
Application No. 08/663,969
microprocessor, and clock circuitry are collocated on the same
chip. A phase locked loop of the clock circuitry receives the
reference clock signal and produces a sense clock signal for
use by the remainder of the chip. The sense clock signal is a
multiple of the reference clock signal. The test circuit
counts the cycles of the sense clock signal that occur within
a predetermined time, which is proportional to the reference
clock’s period. Alternatively, the sense clock signal and the
reference clock signals may be passed through an exclusive-OR
circuit and the cycles counted within a predetermined time.
Either way, if the number of cycles counted is not what was
expected, the sense clock signal is concluded to be incorrect.
Claim 36, which is representative for our purposes,
follows:
36. A method for testing a clock signal
generator in a data processing system, said method
comprising the steps of:
receiving a clock signal;
receiving a reference clock signal; and
determining if transition edges of
said clock signal and said reference clock
signal are substantially aligned by
counting a number of cycles of said clock
signal occurring in a predetermined period
of time.
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