Appeal No. 1997-3818
Application 08/208,517
Claims 1 and 11, the only independent claims, read
as follows:
1. An image processor comprising:
a data processor having a plurality of first address
lines and a plurality of first data lines, said data processor
supplying an address on said plurality of first address lines
and transferring data via said plurality of data lines;
an external port having a plurality of second
address lines, a plurality of second data lines, a plurality
of memory control output lines and a plurality of memory
protocol input lines; and
a static decoder coupled to said memory protocol
input lines of said external port for sampling inputs on said
memory protocol input lines at a predetermined time in a
memory cycle
and for decoding said sampled inputs from said memory protocol
input lines of said external port into memory type signals;
and
memory interface circuitry coupled to said data
processor, said external port and said static decoder
operative to transfer information between said data processor
and said external port, said memory interface circuitry
including:
an addressing means receiving a data processor
address on said plurality of first address lines of said data
processor and supplying said processor address to said
plurality of second address lines of said external port for
output;
a memory-type decoder connected to said static
decoder for selecting a memory protocol for information
4
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