Appeal No. 1997-3818
Application 08/208,517
negates any inference that these memory
size feedback lines 58 to 61 are
sampled at a predetermined time in a memory
access cycle as recited in claim 1. [Brief
at 13.]
The examiner responds that "by using the combination of
address latches, gates and strobe signals, the decoder 52
indeed samples, reads, or obtains the memory size signals to
generate other memory control signals during a memory cycle"
(Answer at 10).
We agree with the examiner and further note that the artisan,
when incorporating Grants' memory size auto-detect feature in
Bowater's system, would realize that the memory module
selection function provided by Grants' latch 48, PROM 52, and
gates 66-69 are not needed in Bowater's system, in which that
function is performed by memory controller 110. In other
words, the artisan would appreciate that it is only necessary
to provide each of Bowater's memory elements with means (e.g.,
a grounded or ungrounded terminal) for producing a signal
representative of the memory size, which signal would then be
sampled under the control of Bowater's microprocessor 100
13
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