Appeal No. 1997-3818
Application 08/208,517
The § 103 rejection of claim 1 is therefore
affirmed, as is the § 103 rejection of dependent claims 2-4,
which are not separately argued.
F. The § 103 rejection of claims 11 and 12
based on Bowater, Grants, and Kinoshita
Claim 11 is directed to the technique of bus size
recognition and selection.
Kinoshita discloses "a simple, low-cost personal
computer having a 32-bit microprocessor compatible with
existing
16-bit personal computer software" (col. 1, lines 35-38).
Referring to Figure 1, peripheral LSIs identified as VLSIA 3
and VLSIB 4 are arranged between MPU (Micro Processing Unit) 1
and various peripheral devices (col. 2, lines 18-26). VLSIA
controls and interfaces between the MPU bus and other devices,
such as external devices and memories (col. 2, lines 36-38).
VLSIA 3 includes a latch 301 and a bus width converter 302,
shown in Figure 2 (col. 5, lines 14-15 and 31-32). As shown
in Figure 3, latch 301 includes drivers/receivers 301 , 301 ,1 3
and 301 for receiving bit groups 16-31, 8-15, and 0-7,
4
15
Page: Previous 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Next
Last modified: November 3, 2007