Appeal No. 1997-3818
Application 08/208,517
memory modules 30-33 include terminals 58-61 which are
connected to ground within the module if the memory size is 1K
and are left unconnected if the memory size is 4K (col. 6,
lines 5-12). These terminals are connected via feedback lines
53-56 to the four least significant address terminals (A-D) of
decoder PROM 52, of which the four most significant address
terminals (E-H) receive address signals AB10-AB13 held in
address latch 48 (col. 5, line 61, to col. 6, line 1). The
four PROM output terminals 65 are connected as inputs to
respective gates 66-69, which are "commonly connected to a
STROBE control line 70 which is driven to a logic high voltage
after an address is clocked into the address latches 45-48"
(col. 6, lines 21-29). The decoder PROM 52 is programmed to
generate a logic high voltage at one of the output terminals
65 when it is addressed, with the result that one of the four
memory modules 30-33 is enabled through its chip select (CS)
and strobe (STR) terminals when an address within the 16K
address range of the memory circuit appears on the address bus
3 (col. 6, lines 30-36). The particular memory enabled is
11
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