Appeal No. 1997-3818
Application 08/208,517
determined by address bus leads AB10-AB13 and the state of the
size feedback lines 53-56 (col. 6, lines 36-39).
The examiner contends that it would have been
obvious "to modify Bowater's memory controller with Grants'
teaching for providing a circuit for auto-detecting [the] type
of memory module used in the system because it would have
further increased the flexibility and versatility of Bowater's
memory controller" (Answer at 6). Appellants argue that
Bowater thus modified will not satisfy claim 1's requirement
for a "static decoder . . . for sampling inputs on said memory
protocol input lines at a pre- determined time in a memory
cycle." Specifically, appellants
argue that Grants fails to disclose (a) taking any samples of
memory protocol input lines and (b) performing such sampling
"at a predetermined time in a memory cycle." Regarding point
(a), appellants submit that Grants
fails to make obvious [the claimed]
sampling of the memory protocol input
lines. Note in Grants et al that the
signals from the memory size feedback lines
58 to 61 of the memory modules 51 are
continuously supplied to decoder PROM 52
via wiring in the circuit board. This
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