Appeal No. 1997-3818
Application 08/208,517
plurality of second address lines of said external port for
output;
a decoding circuit connected to said bus size
input lines for sampling input on said bus size input lines at
a predetermined time in a memory cycle following supply of
said data processor address for decoding said sampled inputs
from said bus size input lines of said external port to
indicate a bus size protocol for transfers of information;
a data circuit supplying data from said data
buffer to a predetermined set of said second address lines of
said external port corresponding to said bus size indicated by
said bus size input lines in a quantity of bits corresponding
to said bus size indicated by said bus size input lines and
supplying no data on other of said second address lines of
said external port.
We note that neither the examiner nor appellants
have explained how each of the limitations of appellants'
claims, including the limitations specifically argued in the
brief (i.e., the "status decoder" of claim 1 and the "decoding
circuit" of claim 11), read on appellants' disclosed
apparatus. The only elements of claims 1 and 11 that have
been read by appellants on their disclosure are the following
(Brief at 2-3):
6
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