Appeal No. 1997-3818
Application 08/208,517
transfer between said data processor and said external port
dependent upon said memory type signals; and
a memory controller connected to said memory type
controller, said first plurality of data lines of said data
processor, said second plurality of data lines and said
plurality of memory control output lines of said external port
for supplying memory control outputs signals to plurality of
memory control output lines of said external port for control
of information transfer between said data processor and said
external port for a next memory cycle corresponding to said
selected memory protocol.
11. A [sic] image processor comprising:
a data processor having a plurality of first address
lines and a plurality of first data lines, said data processor
supplying an address on said plurality of first address lines
and transferring data via said plurality of data lines;
an external port having a plurality of second
address lines, a plurality of second data lines, a plurality
of memory control output lines and a plurality of bus size
input lines; and
a data buffer connected to said first data lines of
said data processor; and
memory interface circuitry coupled to said data
processor, to said external port and to said data buffer
operative to transfer information between said data processor
and said external port, said memory interface circuitry
including:
an addressing means receiving a data processor
address on said plurality of first address lines of said data
processor and supplying said data processor address to said
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